The present invention relates to microelectronic devices and micro-mechanical and micro-electromechanical devices (either type or both types hereinafter, “MEMs”), and more particularly, to a structure and method of providing dummy structures in a layer of material of a substrate during the fabrication of microelectronic devices and MEMs to achieve more uniform developer solution rates, etching rates, and rate at which the height of features of a layer are reduced during planarization processes such as chemical mechanical polishing (CMP)
In the fabrication of microelectronic devices of integrated circuits (ICs) and MEM dies (ICs and MEM dies also referred to herein as “chips”), it is important that certain processes be conducted at uniform rates across the surface of a substrate or wafer on which the chips are fabricated. This is needed despite the fact that the size of layout features and their density may vary from one point to another on the substrate. An example of such process is the development of an exposure pattern in a photoresist layer on a wafer. In such process, a photoresist (hereinafter “resist”) layer is deposited onto a wafer and a photolithographic image is cast on the layer. Thereafter, a developer solution is applied to the resist layer, which chemically reacts with the exposed areas of the resist layer to remove such areas, leaving only the areas that are unexposed by the photolithographic image.
A problem occurs when a resist layer contains features of different densities and sizes. Under such circumstances, the concentration of reactants and reaction products varies from the densely patterned areas to the other areas. As a result, the developer solution used to etch away the exposed areas of the resist layer may etch the resist in the densely patterned areas at a slower rate than in the less densely patterned areas.
The etching of a material layer by a chemical etchant is another process that can vary in uniformity across a wafer depending upon the size and density of features. Again, variation in the size and density of features can cause the concentration of reactants and reaction products to vary, thus making the process nonuniform.
The polishing of material layers of a wafer is yet another process that can vary in uniformity across a wafer, depending upon the size and density of features. Polishing, especially chemical mechanical polishing (CMP) is often used in the fabrication of chips to reduce the topography of features in a material layer. Polishing may also be used to remove excess deposited material from above a patterned feature layer. For example, polishing is used to remove excess oxide after shallow trench isolations are filled and to remove excess metal after filling damascene metallization patterns. Polishing, especially CMP, is used to planarize a material layer.
A goal of such polishing processes is to smooth variations in the topography of features and, in some cases, to smooth a material layer to a uniformly planar surface. Failure to achieve such goals can hinder the function of features in a material layer and/or hinder subsequent processing in a manner that can cause device degradation and reduce yields.
It is known that the density of raised areas in a material layer directly affects the aforementioned rates. For example, it is known that the removal rate of material during polishing is inversely proportional to the surface area of the wafer in contact with the polisher. This surface area is also referred to herein as the “pattern density” which is directly proportional to the area of raised features on a wafer. Such raised features can be, for example, the result of material depositions to fill trenches and/or gaps within a dielectric material, a metal or semiconductor material.
Two chips having different layouts can have different pattern densities, and even one chip can have material layers which vary in pattern density across the chip. Wafers on which such chips are fabricated can themselves have areas near the edge that are smaller than the chip die size, and therefore not have any layout features in such areas. Consequently, CMP processing results in different removal rates in different areas of each such chip or wafer. If the same process is used to polish a corresponding layer of two wafers from which two different types of chips having different pattern densities are formed, results will vary for the two wafers. On the wafer having the greater pattern density, the height of features will be reduced to a lesser extent than the wafer having the lower pattern density.
A number of approaches have been developed in an effort to mitigate the effect of pattern density variations in wafer processing. U.S. Pat. No. 5,639,697 issued Jun. 17, 1997 to Weling et al. describes a method of using dummy structures in pattern layers of a wafer to provide more uniform pattern density across the wafer. The dummy structures serve to raise the pattern density in areas of the wafer. The dummy structures are not electrically active elements of the chip when fabrication is completed. As described in the above-mentioned patent, these dummy structures can be any shape and size and can be placed uniformly or non-uniformly in areas of the wafer. Thus, with the addition of dummy structures, areas of a wafer having different layouts can be made to approximate the same pattern density value to achieve, for example, improved planarization during CMP.
As an alternative, it is also known to use a method known as reverse etchback to reduce the pattern density in some fabrication processes. In this method, pattern density is controlled by removing material from a region of high material density by etching away portions of the raised areas, thus lowering the density (and, therefore, the surface area) of that region.
The article “Using Smart Dummy Fill and Selective Reverse Etchback for Pattern Density Equalization” by Lee et al., Proc. CMP-MIC, pp. 255-258, March 2000, describes another process for controlling pattern density of a layer during fabrication, for example, a shallow trench isolation (STI) fill layer. As described therein, variations in pattern density are reduced through a combination of reverse etchback and addition of dummy structures.
Unfortunately, the above techniques still have limitations with respect to improving the yield and reliability of chip fabrication.